notizie sull'azienda Marvell boosts CXL-connected memory capacity and speed with AI in mind

Marvell has upgraded its memory expansion controllers to boost available memory for AI KV caching workloads.

Once a GPU’s high-bandwidth memory fills with cached key-value data used in AI token processing, workloads spill over into a server’s x86 DRAM, which also hits capacity limits. Compute Express Link (CXL) pools external memory and makes it accessible across the PCIe bus to attached servers and devices, expanding the DRAM KV caching pool. The fabless chip vendor’s existing CXL controllers have advanced beyond their original CXL 2.0 / PCIe Gen5 capabilities, adding CXL v3.2, PCIe Gen6 and additional memory channels.

Will Chu, EVP and GM of Custom Cloud Solutions at Marvell, stated: “Marvell is the only provider with a full end-to-end CXL portfolio covering memory expansion (Structera X), near-memory acceleration (Structera A), and PFMA (Photonic Fabric Memory Appliance), a pod-scale CXL memory-sharing appliance. This delivers customers a complete stack from direct-attached storage to disaggregated memory pooling. We offer industry-leading CXL controllers co-developed with top hyperscalers to meet the strictest AI infrastructure demands.”

Marvell’s first-gen Structera controllers are the X2404 and X2504; the second generation includes X3406 and X3506. The naming convention works as follows:
--First digit: CXL version (2 = CXL 2.0; 3 = CXL 3.x / 3.2).
--Second digit: DDR generation (4 = DDR4; 5 = DDR5).
--Final two digits: memory channel count (04 = 4 channels; 06 = 6 channels).

The X3406 and X3506 deliver these capabilities:
--Expanded AI memory capacity with six DDR4/DDR5 memory channels, a 50% increase over the prior generation, supporting up to 9TB DDR4 or 6TB DDR5 per controller.
--Faster memory-bound AI workloads: up to 5× higher LZ4 compression throughput yields 2–3× greater effective memory capacity, lifting performance for large language model serving and DLRM (Deep Learning Recommendation Model).
--Multi-host support via CXL 3.2, enabling memory sharing across up to four hosts with host bandwidth of 256 GB/s, paired with enterprise-grade RAS and post-quantum security.

Jim Handy, General Director at Objective Analysis, commented: “CXL is seeing broader adoption inside AI systems, which gain major advantages from its high bandwidth and large memory support. Current memory shortages and elevated pricing push IT teams to reuse existing DDR4 DIMMs within DDR5 servers through CXL for quick cost savings. Going forward, teams will leverage CXL memory pools to cut stranded memory waste for further savings, and controllers with built-in compression like this model will grow more appealing.”

Marvell noted its earlier X2404/2504 architecture is already shipping to hyperscalers, and two hyperscalers have endorsed the new product line.

An Alibaba spokesperson said: “Our partnership with Marvell combines its CXL technology leadership and Alibaba’s expertise in large-scale AI and cloud infrastructure to build memory architectures for next-generation AI data centers.”

Yashar Bayani, Meta Director of Hardware Engineering, said: “Meta is glad to collaborate with Marvell to evolve CXL solutions addressing rising memory requirements for compute infrastructure. As systems scale, raising memory capacity while boosting infrastructure efficiency and cost performance becomes essential. CXL offers a flexible method to expand memory resources and improve infrastructure economics, and we look forward to ecosystem collaboration including Marvell to enable next-gen scalable infrastructure.”

Marvell Structera X 3406 and Structera X 3506 CXL memory expansion controllers are scheduled for sampling in Q1 2027.

Comment
Marvell invests heavily in photonics, and we anticipate the launch of external memory pools linked to processors over high-speed photonic connections. CXL will likely integrate photonics primarily by using optical interconnects (silicon photonics and fiber) as the physical transport layer while retaining unchanged CXL protocol, coherency and memory semantics. PCIe Gen6 and Gen7 may also adopt photonic physical transport.

Beijing Qianxing Jietong Technology Co., Ltd.
Sandy Yang/Global Strategy Director
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